High level synthesis tools can create a register-transfer level (RTL) (e.g., VHDL/verilog/systemVerilog) code from high level source code (e.g., C, C++). High level synthesis makes testing and changing RTL hardware efficient because changes can be made into high level source code instead of rewriting RTL which is slow and error prone process. Arithmetic coding can be a complex element of modern video compression standards (e.g., VP8/VP9/HEVC/H264) and debugging/testing of arithmetic coding can be a tedious task if a hardware accelerator is implemented in RTL. To counter this problem high level synthesis is used. However, arithmetic coding can be very data dependent and non-linear algorithm high level synthesis tools can have problems while trying to generate the RTL code from the high level source code.
As a result, high level synthesis of a hardware accelerator typically fails because of failures in synthesizing the arithmetic coding. These failures result in excessive debugging/testing of hardware accelerator designs. Similar complex systems have corresponding drawbacks when sub-elements repeatedly fail during system synthesis resulting in excessive debugging/testing of the system.